Hold-Time Violations. The skunkworks that generate this universe have become faulty, and the physical constants suddenly.aren't. In order to fix the skunkworks, to make physics self-consistent again, and to make the world work as it's supposed to, Ellie will have to remember everything her mother has taught her.
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Setup and Hold time concept is one of the fundamental concepts that is very necessary for closing and analysing and timing margin. The analysis in digital domain, in Reg to Reg system is very popular but the root cause of Setup and Hold time is often not taken care of in the education system. This Post elaborates the cause of setup analysis in a single D latch taking the Transistor level schematic into account, also I will try to explain the points where Setup and Hold time is measured and why we do so and why we can not write it on any other points.Fig.1 Displays a Transistor Level Diagram of a simple D-latch, D is the input and I1, I2 are the inverters in the data path of the latch, T1 is the forward path transmission gate and T2 is the feedback path transmission gate, while LI1 and LI2 are the cross coupled latch inverters. The latch is controlled by the signal CK.Fig.1 A single D LatchFig.2 shows the CK signal used, the CLKdelay is the delay between the rising edge and the falling edge of the CK and CKbar signal.Fig.2 Clock signals used.Setup Analysis1. Setup time is the minimum time required for the data to get settled before the latching edge of the clock in this case it is the Rising edge.2.
The requirement of the setup time arises from the fact that the latching action is performed by the cross coupled inverters LI1 and LI2, the latch is a Bi-Stable which means that is is stable at two points either (0,1) or (1,0)., this implies that if the latch is at any between logic, it can go in either direction, so to have the safest of the operation the logic at point B should be same as the logic at point C. This means any change in data should propagate to point C before the latching action of the latch begins that is closing of the T2 and opening of T1.3.